1. Technical Field
The present invention relates to adaptive design methods and systems, and more particularly to systems and methods for altering designs based on in-situ information obtained during fabrication or during design.
2. Description of the Related Art
As technology scales, memory speed and other performance factors form critical limitations for today's processing systems. Particularly, process variations can impact memory devices and mismatches between neighboring devices of a memory cell can lead to memory fails. This can impact overall chip yield. Statistical techniques to study stand-alone memory cell yield have been proposed in the prior art. However, in practical designs, memory cells interface a hierarchy of complex peripheral logic units for data to be transferred to and from a processor. Hence, the performance and yield of a memory array is not only impacted by cell intrinsic variations and mismatch but is also a function of the in-situ conditions/designs that interface, control and possibly limit the cell yield or overall memory yield.
A very basic example of the in-situ conditioning of a cell would be a sense amplifier sensing level. A requirement of 100 mV bitline difference can lead to a cumulative yield that is different from a 200 mV bitline difference.
In more complex situations where the sense amplifier itself is subject to variability, such variability is unacceptable. While the previous example may be manageable, more complex situations can face the memory designer when variability analysis involves a peripheral logic cross-section and a memory array resulting in a cumulative non-linear impact on the overall memory stability/yield.
Consider the example of false-read before write phenomena. It is possible that the bit select circuitry can turn on early enough before the write control signals such that a strong SRAM cell, due to process variations, can pull-down the bitlines early. This would trigger a false-read, and wrong data may be latched to peripheral circuitry. This involves measuring a glitch, is dependent on the SRAM cell rare fails and cannot be covered by statistical timing tools. On the other hand, it is also a function of the peripheral logic timing and statistics.
While it is possible to throw the entire cross-section into statistical memory analysis tools, in general, peripheral logic cross-sections are often too large to be handled by those tools. At the same time, it is not feasible for timing analysis tools to account for the memory cell when analyzing a peripheral logic circuit. This is particularly true when the analysis involves stability of memory. Even for timing yield, memory cells are often treated as dummy loading units. Furthermore, memory analysis requires fast statistical techniques that are not supported by existing statistical timing methodologies. Timing tools stop at the array boundary.
Hence, stand-alone cell yield can vary based on in-situ analysis of the memory cell. It is too costly to perform yield analysis on a large memory cross-section using existing memory statistical techniques. A transistor level analysis of full cross-section can be too costly. Statistical timing tools cannot accommodate for memory yield analysis (stability, for example). Furthermore, it is often possible to fall into a situation where the cell designer does not have much information about a final peripheral logic circuit design to begin with.